RVCOM is an enhanced yet simplified version of the original RISC-V-Computer.
 
RVCOM has the following features:

  • Redesigned CPU with two versions to choose from a Single-Cycle and 5-Stage-Pipelined
  • Simplified Main Memory module
  • DMA (Direct Memory Access)
  • Redesigned I/O Interface

The original RISC-V Computer was intended to be a practical approach for understanding computer organization and architecture with the help of RISC-V ISA, however the design was overly complicated. Completely redesigned, the new simplified design has a smaller footprint based on Von Neumann arhitecture and both CPUs implements the RV32IM extentions.
 
The pipelined version implements the classical 5-Stage RISC pipeline [IF,ID,EX,MA,WB] and supports hazard detection and operand forwarding.
 
You are going to need a RISC-V C/C++ compiler to load programs and run them on the simulator.

 

You can download RVCOM here