This is another course from Udemy on some advanced topics on the RISC-V ISA.

 

What you’ll learn
  • Understand RISC-V architecture in greater detail, and, as per speculations, this is the architecture which you will find in almost 1 trillion mobile devices.
  • Learn how computers and processors does basic calculations.
  • This course will help understand why RISC-V is the next big thing.
  • This course lays the foundation to do RISC-V software basic labs.
Requirements
  • You should have completed RISC-V ISA Part 1a online course.
  • You should be familiar with boolean addition and subtraction concepts.
  • You should be familiar with number systems
Description

This course is in continuation with my previous course “VSD – RISCV : Instruction Set Architecture (ISA) – Part 1a” which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture – An important one needed in today’s fast changing computing world.

We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.

 

Who this course is for
  • Anyone who wants to learn world’s first Open-Source instruction set architecture RISC-V
  • Anyone who wants to learn how to write specifications for RTL coding
  • Anyone looking forward to implement their own processor using all open-source tools