This is an excellent RISC-V CPU design tutorial for the complete beginner. Written by Hannah McLaughlir, it is divided into two parts where the first part covers basic computer architecture and the second one implements a small RV32I core.

 

Hannah tries to design a single-stage CPU; that is, he is trying to design a CPU that retires one instruction per clock cycle with no pipelining. Usually CPUs have pipelining in place to maximise efficiency. The hope is that avoiding this will result in a simpler design more suitable for learning.

 

You can view the first part here

 

You can view the second part here