RISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. This course will guide you through the various aspects of understanding the RISC-V community ecosystem, RISC-V International, the RISC-V specifications and how to help curate and develop them, and the technical aspects of working with RISC-V both as a developer and end-user.

 

This course is designed for RISC-V enthusiasts, hardware nerds, and anyone else interested in the details of how an open source ISA is breaking down barriers and opening up new opportunities in the microprocessor world.

 

In this course, you will learn about the nature, history, ongoing practices and other fundamentals of RISC-V as a technology, an international organization, and a community of developers and implementers. You will also see how RISC-V technical working groups are organized, as well as explore the basis of community-based open specification development, and how the RISC-V ISA is developed as an open specification. Moreover, you will learn how people and organizations can benefit from and contribute to RISC-V, and will be able to put the RISC-V ISA into action with a simulator booting the Linux operating system.

 

This course contains a high level overview of RISC-V International as well as how to get started working with the RISC-V ISA. The course gives you the foundation of knowledge you need to effectively engage in the RISC-V community, contribute to the ISA specifications, or to develop the wide range of RISC-V software projects. After completing this course you will have a better understanding of the terminology, resources, and workflow you will need to complete your RISC-V journey.

 

Course Outline
  • Welcome!
  • Chapter 1. Getting to Know RISC-V
  • Chapter 2. The RISC-V Story
  • Chapter 3. The RISC-V Community
  • Chapter 4. Developing RISC-V
  • Chapter 5. RISC-V in Practice
  • Final Exam (verified track only)

 

You can access this course here