The T-Head XuanTie E902 is a fully synthesizable, microcontroller-class processor that is compatible with the RISC-V RV32E[M]C ISA. It delivers ultra-low area and power aiming at the Low end MCUs and loT applications. E902 adopts 2-stage extremely simple pipeline and enhances its execution efficiency and can enhance system security by the optional secure execution environment. It is applicable to IoT, MCU and other areas that are extremely sensitive to power consumption and cost.

 

Features Description
Architecture RV32E[M]C
Bus interface AMBA3 AHB-Lite 32-bit master
Pipeline 2-stages
Security T-Head TEE technology
Instruction cache Up to 8KB
Interrupts 240 interrupts and Non-maskable (NMI)
Sleep modes Sleep and deep sleep mode
Debug 2-wire/JTAG debug port, Hardware and software
breakpoints

 

Processor Overview

The E902 processor adopts a 16/32 bits mixed instruction set and implements an energy-efficient 2-stage, single issue and in-order execution integer pipeline. Besides, E902 customizes four functional instructions and some extend CSRs to support the extensions. The E902 processor supports the T-Head TEE technology which makes E902 suitable for the 10T application which needs to protect the sensitive information.

 

Instruction Cache

E902 implements an optional instruction cache which can cache the data from the instruction bus such as Flash or I-SRAM. The instruction cache has following features:

 

  • 2-way set-associative
  • FIFO cache replacement policy
  • Can be configured to 2KB/4KB/8KB

 

Physical Memory Protection (PMP)

The E902 processor has optional RISC-V PMP which allows machine and user privilege modes to access different address ranges. Only the machine mode has the authority to define the memory access permissions. If an authorized access is detected, an access fault exception is triggered. The PMP has following features:

 

  • Up to 16 regions can be configured
  • Read/Write/Execution memory protection
  • Minimum 4KB address range

 

When TEE is configured, the PMP unit can import more scenarios according to the security of the core.

 

Core Local Interrupt Controller (CLIC)

The E902 processor implements the RISC-V standard interrupt controller, CLIC and the CLINT. The CLIC has following features:

 

  • Support up to 240 external interrupts;
  • Up to 32 priority settings;
  • Support level or positive/negative edge interrupt types;
  • Support hardware vector interrupt
  • The control registers are memory mapped

 

Debug Components

The E902 processor adopts T-Head customized 2-wire debug port or standard JTAG to communicate the host and E902 debug unit. The debug unit supports following operations:

 

  • Support hardware/software breakpoint
  • Support hardware watchpoint
  • Check and modify CPU register resource
  • Single step or multi step flexibly supported
  • Speed up program download through 2-wire debug port or standard JTAG port

 

Interface

The E902 has two 32-bit AMBA3 AHB-Lite master bus to communicate with the external memory or peripheral IP which are instruction and system bus. The internal request can be allocated to either bus according to the address.

 

You can license the T-HEAD E902 RISC-V IP here